1. Field of the Invention
The present invention relates to a low-noise differential bias circuit and a differential signal processing apparatus. More particularly, the present invention relates to a low-noise differential bias circuit for supplying a low-noise direct-current voltage to transistors having a differential configuration, and a differential signal processing apparatus using such a bias circuit.
2. Description of the Related Art
With a rapid increase in the use of wireless communication apparatuses such as mobile phones, there is an increasing need for miniaturization of the functioning section (radio circuit section) where a radio signal is processed. Thus, in the wireless communication apparatus field, the recent trend is to fabricate the radio circuit section into an integrated circuit (IC). To do so, it is necessary to fabricate an amplifier, an oscillator, etc., which are conventionally fabricated as separate individual components or modules, into an IC.
FIGS. 23 and 24 are diagrams illustrating circuit configurations of conventional differential signal processing apparatuses (differential amplification apparatuses) (see Japanese Laid-Open Patent Publications No. 2003-133862 and No. 2003-209446).
A conventional differential signal processing apparatus 501 shown in FIG. 23 is composed of a bias circuit 511 and a differential amplification circuit 521. The bias circuit 511 includes resistors R111 to R114 and an NPN bipolar transistor Q111. The differential amplification circuit 521 includes NPN bipolar transistors Q1 to Q4 and a bias circuit b.
In the differential amplification circuit 521, differential signals (IN) are inputted to the bases of the transistors Q1 and Q2, respectively. In addition, a predetermined bias current is supplied to the base of each of the transistors Q1 and Q2 by the bias circuit 511. The emitters of the transistors Q1 and Q2 are both grounded. The emitters of the transistors Q3 and Q4 are connected to the collectors of the transistors Q1 and Q2, respectively. A predetermined potential is supplied to the base of each of the transistors Q3 and Q4 by the bias circuit b.
In the bias circuit 511, the collector of the transistor Q111 is connected to a voltage supply point (Vcc) via the resistor R114. The base of the transistor Q111 is connected to a collector (connection point E) via the resistor R113. The collector (connection point E) of the transistor Q111 is connected to both the base of the transistor Q1 of the differential amplification circuit 521 via the resistor R111, and the base of the transistor Q2 of the differential amplification circuit 521 via the resistor R112. The emitter of the transistor Q111 is grounded.
A conventional differential signal processing apparatus 502 shown in FIG. 24 is composed of a bias circuit 512 and a differential amplification circuit 521. The bias circuit 512 includes resistors R111 and R112, NPN bipolar transistors Q111 and Q112, and bypass capacitors C111 and C112. The differential amplification circuit 521 is the same as that described above.
The collector of the transistor Q111 is connected to a voltage supply point (Vcc) and the emitter of the transistor Q111 is grounded through the bypass capacitor C111. The collector of the transistor Q112 is connected to the voltage supply point (Vcc) and the emitter of the transistor Q112 is grounded through the bypass capacitor C112. A predetermined reference voltage (Vref) is supplied to the base of each of the transistors Q111 and Q112. The emitter of the transistor Q111 is connected to the base of the transistor Q1 of the differential amplification circuit 521 via the resistor R111. The emitter of the transistor Q112 is connected to the base of the transistor Q2 of the differential amplification circuit 521 via the resistor R112.
By the above-described configurations, the conventional differential signal processing apparatuses 501 and 502 amplify differential signals inputted to the bases of the transistors Q1 and Q2, and then output the amplified signals (OUT) from the collectors of the transistors Q3 and Q4.
The bias circuits 511 and 512 used in the conventional differential signal processing apparatuses 501 and 502 are generally suitable for use in circuits which handle low-frequency signals. Thus, if the bias circuits 511 and 512 are used as they are in circuits which handle high-frequency signals, in particular, in radio circuits which require low noise, the following problems occur.
In the conventional differential signal processing apparatus 501, since the differential signals inputted to the bases of the transistors Q1 and Q2 are canceled at the connection point E through the resistors R111 and R112, the connection point E can be considered as an imaginary high-frequency ground point. However, because of the imaginary ground, if the values of the resistors R111 and R112 are low, a noise component easily flows into the bases of the transistors Q1 and Q2 from the connection point E, degrading noise characteristics. On the other hand, if the values of the resistors R111 and R112 are high, distortion characteristics are degraded due to nonlinearity of input and output signals. Since the allowable voltage drop in the resistors R111 and R112 is determined by the voltage of the voltage supply point, the values of the resistors R111 and R112 cannot be made very high.
In the conventional differential signal processing apparatus 502, the differential signal inputted to the base of the transistor Q1 is grounded through the resistor R111 and the capacitor C111, and the differential signal inputted to the base of the transistor Q2 is grounded through the resistor R112 and the capacitor C112. Therefore, the emitters (connection points F) of the transistors Q111 and Q112 can be considered as imaginary high-frequency ground points. Thus, as in the above-described differential signal processing apparatus 501, if the values of the resistors R111 and R112 are low, noise characteristics are degraded, and if the values of the resistors R111 and R112 are high, distortion characteristics are degraded. Further, since the differential signal processing apparatus 502 includes therein the capacitors C111 and C112, the chip area increases when the differential signal processing apparatus 502 is fabricated into an IC.
As described above, since there is a tradeoff relationship between noise characteristics and distortion characteristics, the bias circuits 511 and 512 of the conventional differential signal processing apparatuses 501 and 502 cannot be simply applied to circuits which handle high-frequency signals. Accordingly, in the wireless communication apparatus field, there is a need to design a novel low-noise bias circuit for high-frequency signals which has excellent noise characteristics and excellent distortion characteristics.